PRELIMINARY
FastEdge鈩?Series
CY2DP3120
1:20 Differential Clock Buffer/Driver
Features
鈥?Twenty ECL/PECL differential outputs
鈥?Two ECL-/PECL-/HSTL-compatible differential clock
inputs
鈥?Hot-swappable/-insertable
鈥?50-ps output-to-output skew
鈥?500-ps device-to-device skew
鈥?Less than 10-ps intrinsic jitter
鈥?< 500-ps propagation delay (typical)
鈥?Operation from DC to 1.5 GHz
鈥?PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
鈥?ECL mode supply range: V
EE
= 鈥?.375V to 鈥?.465V with
V
CC
= 0V
鈥?Industrial temperature range: 鈥?0擄C to 85擄C
鈥?52-pin 1.4-mm TQFP package
鈥?Temperature compensation like 100K ECL
Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device is fully differential and features two reference input
buffers. The CY2DP3120 may function not only as a differ-
ential clock buffer but also as a signal level translator and
fanout distributing a single-ended signal to twenty ECL/PECL
differential loads. An external bias pin, VBB, is provided for an
ECL/PECL/HSTL single-ended or differential. In such an appli-
cation, the VBB pin should be connected to either one of the
CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-碌F
capacitor. Traditionally, in ECL, it is used to provide the
reference level to a receiving single ended input that might
have a different self bias point.
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
Pin Configuration
CLKA
CLKA#
VEE
VCC
0
VEE
VCC
Q0
Q0#
VCCO
VCC
CLK_SEL
CLKA
CLKA#
52 51 50 49 48 47 46 45 44 43 42 41 40
39
1
38
2
37
3
4
5
6
7
8
9
10
11
12
36
35
34
VCCO
Q0#
Q1#
Q2#
Q3#
Q4#
Q5#
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Q10
Q10#
Q11
Q11#
VCCO
CLKB
CLKB#
VEE
VEE
1
Q19
Q19#
VBB
VBB
CLKB
CLKB#
VEE
Q19#
Q19
Q18#
Q18
CY2DP3120
33
32
31
30
29
28
CLK_SEL
VEE
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VCCO
Q17#
Q16#
Q15#
Q14#
Q13#
Q12#
Q17
Q16
Q15
Q14
Q13
Q12
Cypress Semiconductor Corporation
Document #: 38-07514 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 16, 2003
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