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CY29774 Datasheet

  • CY29774

  • Clocks and Buffers

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774
CY29774
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
Features
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Output frequency range: 8.3 MHz to 125 MHz
Input frequency range: 4.2 MHz to 62.5 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 ps max output-output skew
PLL bypass mode
Spread Aware鈩?/div>
Output enable/disable
Pin compatible with MPC9774
Industrial temperature range: 鈥?0擄C to +85擄C
52-Pin 1.0-mm TQFP package
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see
Functional
Table.
These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50鈩?series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see
Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
Block Diagram
Pin Configuration
V C O _S E L
P L L_ E N
TC LK _ S EL
TC LK 0
T C LK 1
FB _IN
VCO_SEL
VDDQC
QC0
VDDQC
QC2
QB0
VDDQB
QC1
QC3
VSS
VSS
VSS
NC
PLL
20 0 -
5 00M H z
梅2
梅4
梅
2 /
梅
4
CLK
S TO P
SELA
梅2
/
梅4
CLK
STOP
Q A0
Q A1
Q A2
Q A3
Q A4
QB0
QB1
Q B2
QB3
QB4
QC0
QC1
QC2
QC3
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
CY29774
S E LB
梅4
/
梅6
CLK
STOP
S E LC
C LK _ S TP #
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL0
AVSS
VDDQA
QA4
QA3
VSS
QA2
FB_SEL1
VDDQA
QA1
VSS
VDDQA
QA0
梅4
/
梅6
/
梅8
/
梅12
F B _O U T
F B _S E L(1,0)
M R #/O E
Cypress Semiconductor Corporation
Document #: 38-07479 Rev. **
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised April 28, 2003

CY29774相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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    描述
    廠商
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  • 英文版
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  • 英文版
    Single-PLL General-Purpose EPROM Programmable Clock Generato...
    CYPRESS [C...
  • 英文版
    Single-PLL General-Purpose EPROM Programmable Clock Generato...
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    3.3V 125-MHz 8-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS [C...

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