錚?/div>
CK410M
鈥?Supports Intel Pentium-M CPU
鈥?Selectable CPU frequencies
鈥?Differential CPU clock pairs
鈥?100-MHz differential SRC clocks
鈥?96-MHz differential dot clock
鈥?48-MHz USB clocks
鈥?SRC clocks independently stoppable through
CLKREQ#[A:B]
鈥?96/100 MHz Spreadable differential clock.
鈥?33-MHz PCI clock
鈥?Low-voltage frequency select input
鈥?I
2
C support with readback capabilities
鈥?Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
鈥?3.3V power supply
鈥?56-pin TSSOP package
CPU
x2 / x3
SRC
x5/6
PCI
x6
REF
x2
DOT96
x2
USB_48
x1
Block Diagram
VDD_REF
REF
IREF
VDD_CPU
CPUT
CPUC
VDD_CPU
CPUT_ITP/SRCT7
CPUC_ITP/SRCC7
VDD_SRC
SRCT[1:5]
CPUC[1:5]
VDD_PCI
PCI
VDD_PCI
PCIF
PLL2
96MSS
VDD_48MHz
96_100_SSCT
96_100_SSCC
VDD_48MHz
DOT96T
DOT96C
VDD_48
VTTPWR_GD#/PD
USB
Pin Configuration
XIN
XOUT
PCI_STP#
CPU_STP#
CLKREQ[A:B]#
FS_[C:A]
14.318MHz
Crystal
PLL Reference
PLL1
CPU
Divider
Divider
PLL4
FIXED
Divider
VDD_REF
VSS_REF
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
ITP_EN/PCIF0
**96_100_SEL/PCIF1
VTTPWRGD#/PD
VDD_48
FS_A/48M_0
VSS_48
DOT96T
DOT96C
FS_B/TESTMODE
96_100_SSCT
96_100_SSCC
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2/SEL_CLKREQ**
PCI_STP#
CPU_STP#
FS_C(TEST_SEL)/REF0
REF1
VSSA2
XIN
XOUT
VDDA2
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7
VDD_SRC_ITP
CLKREQA#/SRCT6
CLKREQB#/SRCC6
SRCT5
SRCC5
VSS_SRC
56 pin TSSOP/SSOP
SDATA
SCLK
I2C
Logic
Cypress Semiconductor Corporation
Document #: 38-07680 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 24, 2004
CY28442
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