音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY28408ZC Datasheet

  • CY28408ZC

  • Clock Synthesizer with Differential CPU Outputs

  • 213.45KB

  • 19頁(yè)

  • CYPRESS

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

CY28408
Clock Synthesizer with Differential CPU Outputs
Features
鈥?Compatible to Intel
廬
CK 408 Mobile Clock Synthesizer
鈥?Support Intel P4 and Brookdale CPU
鈥?Specifications
鈥?3.3V power supply
鈥?Three differential CPU clocks
鈥?Ten copies of PCI clocks
Table 1. Frequency Table
[1]
S2
1
1
1
1
0
0
0
0
M
M
S1
0
0
1
1
0
0
1
1
0
0
S0
0
1
0
1
0
1
0
1
0
1
133 MHz
Hi-Z
TCLK/2
66 MHz
Hi-Z
TCLK/4
166 MHz
66 MHz
100 MHz
66 MHz
66 MHz
66 MHz
CPU(0:2)
100 MHz
133 MHz
3V66
66 MHz
66 MHz
PCI_PCIF
33 MHz
33 MHz
Reserved
33 MHz
33 MHz
33 MHz
Reserved
33 MHz
Hi-Z
TCLK/8
14.318 MHz
Hi-Z
TCLK
48 MHz
Hi-Z
TCLK/2
14.318 MHz
14.318 MHz
14.318 MHz
48 MHz
48 MHz
48 MHz
REF
14.318 MHz
14.318 MHz
USB/DOT
48 MHz
48 MHz
鈥?Six copies of 3V66 clocks
鈥?SMBus support with read back capabilities
鈥?Spread Spectrum electromagnetic interference (EMI)
reduction
鈥?Dial-A-Frequency
廬
features
鈥?Dial-A-dB錚?features
鈥?56-pin TSSOP package
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PWRGD#
PCI_STP#
PLL2
WD
Logic
I2C
Logic
Power
Up Logic
/2
Pin Configuration
REF
CPUT(0:2)
CPUC(0:2)
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
EPCI1/PCI1
PCI2
EPCI3/PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
3V66_2
3V66_3
3V66_4
3V66_5
PD#
VDDA
VSSA
VTT_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPUT0
CPUC0
VDD
CPUT1
CPUC1
VSS
VDD
CPUT2
CPUC2
MULT0
IREF
VSSIREF
S2
48M_USB
48M_DOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
3V66_0
3V66_1/VCH
PCI(0:6)
PCI_F(0:2)
48M_USB
48M_DOT
CY28408
PD#
SDATA
SCLK
VDDA
3V66[2:5]
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, an
0 state will be latched into the device鈥檚 internal state register.
Cypress Semiconductor Corporation
Document #: 38-07617 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 17, 2003

CY28408ZC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS [C...
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clock Generator for Serverworks Grand Champion Chipset Appli...
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for VIA PL133T and PLE133T
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for Intel? Pentium? 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS [C...
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線(xiàn)人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線(xiàn)時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！