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CY28405-2 Datasheet

  • CY28405-2

  • Clocks and Buffers

  • 48頁

  • ETC

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CY28405-2
Clock Synthesizer with Differential SRC and CPU Outputs
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports Intel
錚?/div>
Pentium
廬
4-type CPUs
Selectable CPU frequencies
3.3V power supply
Nine copies of PCI clocks
Four copies of 3V66 with one optional VCH
Two copies 48-MHz clock
鈥?/div>
鈥?/div>
鈥?/div>
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Three differential CPU clock pairs
One differential SRC clock
Support SMBus/I
2
C Byte, Word and Block Read/ Write
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
鈥?/div>
48-pin SSOP package
CPU
x3
SRC
x1
3V66
x4
PCI
x9
REF
x2
48M
x2
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF(0:1)
VDD_CPU
CPUT(0:1, ITP), CPUC(0:1, ITP)
VDD_SRCT
SRCT, SRCC
[1]
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
FS_(A:B)
VTT_PWRGD#
IREF
VDD_3V66
3V66_(0:2)
PLL2
2
VDD_PCI
PCIF(0:2)
PCI(0:5)
3V66_3/VCH
PD#
VDD_48MHz
DOT_48
USB_48
SDATA
SCLK
I
2
C
Logic
*FS_A/REF_0
*FS_B/REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PD#
DOT_48
USB_48
VSS_48
VDD_48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
IREF
CPUT_ITP
CPUC_ITP
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
SDATA*
SCLK*
3V66_0
3V66_1
VSS_3V66
VDD_3V66
3V66_2
3V66_3/VCH
~
SSOP-48
* 100k Internal Pull-up
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07511 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised Spetember 29, 2003
CY28405-2

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