鈥?/div>
鈥?8 Low-skew/jitter PCI clocks
鈥?2 Low-skew/jitter fixed PCI clocks
鈥?1 48M output for USB
鈥?1 Programmable 24M or 48M for SIO
鈥?2 REF 14.318 MHz
Dial-a-Frequency
廬
and Dial-a-dB
廬
features
Spread spectrum for best EMI reduction
SMBus compatible for programmability
56-pin SSOP package
Block Diagram
Pin Configuration
[1]
VSSREF
*MULSEL/REF0
**FS2/REF1
VDDREF
XIN
XOUT
VSSPCI
**FS4/PCI_F0
**FS3/PCI_F1
VDDPCI
VSSPCI
PCI0
PCI1
PCI2
VDDPCI
VSSPCI
PCI3
PCI4
PCI5
VDDPCI
PCI6/*PCI_STP#
PCI7/*CPU_STP#
SDATA
VSS48
**FS0/48M
**FS1/24_48M
VDD48
*VTT_PWRGD/*PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDMREF
MREF
MREF_B
VSSMREF
SCLK
CPUT3
CPUC3
VDDCPU
CPUT2
CPUC2
VSSCPU
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
VSSCPU
IREF
VDDA
VSSA
VDDAGP
AGP1
AGP0
VSSAGP
VDDZ
ZCLK1
ZCLK0/*MODE
VSSZ
XIN
XOUT
PLL1
CPU_STP#
IREF
FS(0:4)
MULSEL
VTTPWRGD
PCI_STP#
PLL2
Power
on
Latch
REF(0:1)
CPUT(0:3)
CPUC(0:3)
MREF/
MREFB
AGP(0:1)
ZCLK(0:1)
PCI(0:7)
PCI_F(0:1)
48M
48M_24M
PD#
SDATA
SCLK
PwrDn
Logic
I2C
Logic
Note:
1. Pins marked with [*] have 200-K鈩?internal pull-up resistors. Pins marked with [**] have 200-K鈩?internal pull-down resistors
Cypress Semiconductor Corporation
Document #: 38-07460 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 18, 2002
CY28373
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