CY28372OC Datasheet

IC型號：
CY28372OC
PDF描述：
SiS 746 AMD Athlon/AMD Duron Clock Synthesizer
文件大小：
284.32KB
PDF頁數(shù)：
18頁
芯片廠家：
CYPRESS

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CY28372

SiS 746 AMD Athlon鈩?AMD Duron鈩?Clock Synthesizer

Features

鈥?/div>

Supports AMD Athlon錚?Duron錚?CPU

鈥?3.3V and 2.5V power supply

鈥?Eight copies of PCI clocks

鈥?One 48-MHz USB clock

鈥?Two copies of ZCLK clocks

鈥?One 48-MHz/24-MHz programmable SIO clock

鈥?One differential CPU clock (opendrain)

鈥?One singled-ended CPU clock (opendrain)

鈥?SMBus support with readback capabilities

鈥?Spread Spectrum electromagnetic interference (EMI)

reduction

鈥?/div>

48-pin SSOP package

CPU

ZCLK

REF

PCI

AGP

IOAPIC

48M

24_48M

Block Diagram

XIN

XOUT

Pin Configuration

PLL Ref Freq

Divider

Network

VDD_REF

REF0:2

VDD_CPU

CPUT1

CPUT0, CPUC0

VDD_Z

ZCLK0:1

XTAL

OSC

PLL 1

**FS0:3

CPU_STP#

VDD_APIC

APIC0:1

VDD_PCI

PCIF0:1

PCI0:5

PCI_STP#

Fract.

Aligner

VDD_AGP

AGP0:1

PLL2

PD#

VDD_48

48 MHz

24_48MHz

VDD_REF

**FS0/REF0

**FS1/REF1

REF2

GND_REF

XIN

XOUT

GND_Z

ZCLK0

ZCLK1

VDD_Z

*PCI_STP#

VDD_PCI

**FS2/PCIF0

*FS3/PCIF1

PCI0

PCI1

GND_PCI

VDD_PCI

PCI2

PCI3

PCI4

PCI5

GND_PCI

VDD_APIC

IOAPIC1

IOAPIC0

GND_APIC

CPU_STP#*

CPUT1

VDD_CPU

GND_CPU

CPUT0

CPUC0

VDD_CPU

GNDA

VDDA

SCLK

SDATA

PD#*

GND_AGP

AGP0

AGP1

VDD_AGP

VDD_48

48MHZ

24_48MHZ

GND_48

SDATA

SCLK

I2C

Logic

SSOP-48

* : Internal Pull-up 150k

** : Internal Pull-down 150k

Cypress Semiconductor Corporation

Document #: 38-07533 Rev. *A

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

CA 95134

鈥?/div>

408-943-2600

Revised September 20, 2004

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CY28372OC Datasheet

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