音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY28358 Datasheet

  • CY28358

  • Clocks and Buffers

  • 11頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

58
PRELIMINARY
CY28358
200-MHz Differential Clock Buffer/Driver
Features
鈥?Up to 200 MHz operation
鈥?Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
鈥?Distributes one clock input to six differential outputs
鈥?External feedback pin FBIN is used to synchronize the
outputs to the clock input
鈥?Conforms to the DDR1 specification
鈥?Spread Aware鈩?for EMI reduction
鈥?28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the feed-
back clock FBIN.
The two line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test purpos-
es.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low鈥搄itter output differential clocks.
Block Diagram
Pin Configuration
10
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKIN
NC
AVDD
AGND
VDD
CLKT2
CLKC2
CY28358
CLKT0
CLKC0
CLKT1
CLKC1
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKIN
PLL
FBIN
CLKT4
CLKC4
CLKT5
CLKC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
AVDD
FBOUT
28 pin SSOP
Cypress Semiconductor Corporation
Document #: 38-07417 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002

CY28358相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS [C...
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clock Generator for Serverworks Grand Champion Chipset Appli...
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for VIA PL133T and PLE133T
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for Intel? Pentium? 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS [C...
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！