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CY28352 Datasheet

  • CY28352

  • Clocks and Buffers

  • 8頁

  • ETC

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CY28352
Differential Clock Buffer/Driver
DDR400- and DDR333 Compliant
Features
鈥?Supports 333-MHz and 400-MHz DDR SDRAM
鈥?60- 鈥?200-MHz operating frequency
鈥?Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
鈥?Distributes one clock input to six differential outputs
鈥?External feedback pin FBIN is used to synchronize
output to clock input
鈥?Conforms to DDRI specification
鈥?Spread Aware錚?for electromagnetic interference (EMI)
reduction
鈥?28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
DD
is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low鈥搄itter output differential clocks.
Block Diagram
Pin Configuration
10
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKIN
NC
AVDD
AGND
VDD
CLKT2
CLKC2
CY28352
CLKT0
CLKC0
CLKT1
CLKC1
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKIN
PLL
FBIN
CLKT4
CLKC4
CLKT5
CLKC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
AVDD
FBOUT
28 pin SSOP
Cypress Semiconductor Corporation
Document #: 38-07371 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised May 23, 2003

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