CY28326 Datasheet

IC型號：
CY28326
PDF描述：
FTG for VIA PT880 Serial Chipset
文件大小：
289.34KB
PDF頁數(shù)：
23頁
芯片廠家：
CYPRESS

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CY28326

FTG for VIA PT880 Serial Chipset

Features

鈥?/div>

Supports P4

錚?/div>

CPUs

3.3V power supply

Ten copies of PCI clocks

One 48 MHz USB clock

Two copies of 25 MHz for SRC/LAN clocks

One 48 MHz/24 MHz programmable SIO clock

鈥?Three differential CPU clock pairs

鈥?SMBus support with Byte Write/Block Read/Write

capabilities

鈥?Spread Spectrum EMI reduction

鈥?Dial-A-Frequency

廬

features

鈥?Auto Ratio features

鈥?48-pin SSOP package

Block Diagram

XIN

XOUT

PLL1

CPU_STP#

IREF

Power

Latch

Pin Configuration

[1]

REF[0:2]

CPUT[0:2]

CPUC[0:2]

25MHz[0:1]

AGP[0:2]

FS[A:D]

VTTPWRGD#

PCI_STP#

**FSA/REF0

**FSB/REF1

VDDREF

XIN

XOUT

VSSREF

*FSC/PCIF0

*FSD/PCIF1

*Mode/PCIF2

VDDPCI

VSSPCI

PCI0

PCI1

PCI2

PCI3

PCI4

VDDPCI

VSSPCI

*(PCI_STP#)/Ratio0/PCI5

*(CPU_STP#)/Ratio1/PCI6

48MHz

**24_48_SEL/24_48MHz

VSS48

VDD48

VDDA

VSSA

IREF

CPUT2

CPUC2

VSSCPU

CPUT1

CPUC1

VDDCPU

CPUT0

CPUC0

VSSSRC

25MHz1

25MHz0

VDDSRC

*VTT_PWRGD/*PD#

ATA

SCLK

SRESET#

AGP2

VSSAGP

VDDAGP

AGP1/*RatioSel

AGP0

CY2 8 3 2 6

PCI[0:6]

PCI_F[0:2]

PLL2

MODE

PD#

SDATA

SCLK

Logic

I2C

Logic

48MHz

24_48MHz

SRESET

48 Pin SSOP

Note:

1. Pins marked with [*] have internal 150k鈩?pull-up resistors. Pins marked with [**] have internal 150k鈩?pull-down resistors.

Cypress Semiconductor Corporation

Document #: 38-07616 Rev. *A

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

CA 95134

鈥?/div>

408-943-2600

Revised June 22, 2004

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