CY28322 Datasheet

IC型號：
CY28322
PDF描述：
Clocks and Buffers
文件大小：
237.52KB
PDF頁數(shù)：
17頁
芯片廠家：
ETC

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PRELIMINARY

CY28322-2

133-MHz Spread Spectrum Clock Synthesizer with

Differential CPU Outputs

Features

鈥?Compliant with Intel CK-Titan and CK-408 clock

synthesizer/driver specifications

鈥?Multiple output clocks at different frequencies

鈥?Two pairs of differential CPU outputs, up to 200 MHz

鈥?Nine synchronous PCI clocks, three free-running

鈥?Six 3V66 clocks

鈥?Two 48-MHz clocks

鈥?One reference clock at 14.318 MHz

鈥?One VCH clock

鈥?Spread Spectrum clocking (down spread)

鈥?Power-down features (PCI_STOP#, CPU_STOP#

PWR_DWN#)

鈥?48-pin TSSOP package

Enables reduction of EMI and overall system cost

Enables ACPI-compliant designs

錚?/div>

Benefits

Supports next generation Pentium

錚?/div>

processors using

differential clock drivers

Motherboard clock generator

鈥?Support multiple CPUs and a chipset

鈥?Support for PCI slots and chipset

鈥?Supports AGP, DRCG reference, and Hub Link

鈥?Supports USB host and graphic controllers

鈥?Supports ISA slots and I/O chip

鈥?Two select inputs (Mode select & IC Frequency Select)

Supports up to four CPU clock frequencies

Widely available, standard package enables lower cost

Logic Block Diagram

VDD_REF

PWR

Pin Configurations

TSSOP

Top View

XTAL_IN

XTAL_OUT

GND_REF

PCI_F0

PCI_F1

Stop

Clock

Control

XTAL

OSC

VDD_REF

REF0

CPU_STOP#

VDD_CPU

CPU1

CPU#1

GND_CPU

VDD_CPU

CPU2

CPU#2

IREF

USB

DOT

VDD_48 MHz

GND_48 MHz

3V66_1/VCH

PCI_STOP#

3V66_0

VDD_3V66

GND_3V66

SCLK

SDATA

REF

PLL Ref Freq

PLL 1

S1:2

PWR_GD#

CPU_STOP#

Gate

Divider

Network

PWR

VDD_CPU

CPU1:2

CPU#1:2

PCI_F2

GND_PCI

PCI0

PCI1

PCI2

VDD_PCI

PCI3

PCI4

PCI5

CY28322-2

PWR

Stop

Clock

Control

VDD_PCI

PCI_F0:2

PCI0:5

PCI_STOP#

PWR_DWN#

PWR

VDD_3V66

3V66_0:1

PWR

VDD_3V66

GND_3V66

66BUFF0/3V66_2

66BUFF1/3V66_3

66BUFF2/3V66_4

66IN/3V66_5

PWR_DWN#

VDD_CORE

GND_CORE

PWR_GD#

3V66_2:4/

66BUFF0:2

3V66_5/ 66IN

PLL 2

VDD_48MHz

PWR

USB (48MHz)

DOT (48MHz)

VCH_CLK/ 3V66_1

SDATA

SCLK

SMBus

Logic

Cypress Semiconductor Corporation

Document #: 38-07145 Rev. *B

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

鈥?/div>

CA 95134 鈥?408-943-2600

Revised December 14, 2002

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