CY28316
FTG for VIA PL133T and PLE133T
Features
鈥?Single-chip system frequency synthesizer for VIA
PL133T and PLE133T chipsets
鈥?Programmable clock output frequency with less than
1 MHz increment
鈥?Integrated fail-safe Watchdog Timer for system
recovery
鈥?Automatically switches to HW-selected or
SW-programmed clock frequency when Watchdog
Timer time-out occurs
鈥?Capable of generating system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
鈥?Supports SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
鈥?Vendor ID and Revision ID support
鈥?Programmable drive strength for SDRAM and PCI
output clocks
鈥?Programmable output skew for CPU, PCI, and SDRAM
鈥?Maximized electromagnetic interference (EMI)
suppression using Cypress鈥檚 Spread Spectrum
technology
鈥?Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
Block Diagram
VDD_REF
REF0
X1
X2
XTAL
OSC
REF1/FS2*
Pin Configuration
VDD_REF
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
VDD_PCI
SDRAMIN
GND_SDRAM
SDRAM11
SDRAM10
VDD_SDRAM
SDRAM9
SDRAM8
GND_SDRAM
SDATA
SMBus SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
[1]
PLL Ref Freq
VTTPWRGD#
PLL 1
梅2,3,4
CPU0:1
VDD_PCI
PCI0/FS4*
PCI1/FS3*
PCI2:6
SDATA
SCLK
SMBus
Logic
Reset
Logic
PLL2
梅2
RST#
VDD_48MHz
48MHz/FS0*
{
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VTT_PWRGD#
REF0
REF1/FS2*
GND_CPU
CPU0
CPU1
VDD_CPU
RST#
SDRAM_12
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
SDRAM6
SDRAM7
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
CY28316
SDRAMIN
13
24_48MHz/FS1*
VDD_SDRAM
SDRAM0:12
Note:
1. Signals marked with 鈥?鈥?have internal pull-up resistors.
Cypress Semiconductor Corporation
Document #: 38-07125 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 14, 2002
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