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CY28312B-2 Datasheet

  • CY28312B-2

  • Clocks and Buffers

  • 17頁(yè)

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CY28312B-2
FTG for VIA鈩?K7 Series Chipset with
Programmable Output Frequency
Features
鈥?Single-chip FTG solution for VIA鈩?K7 Series chipsets
鈥?Programmable clock output frequency with less than
1-MHz increment
鈥?Integrated fail-safe Watchdog timer for system
recovery
鈥?Automatically switch to HW-selected or
SW-programmed clock frequency when Watchdog
timer time-out
鈥?Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
鈥?Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
鈥?Vendor ID and Revision ID support
鈥?Programmable drive strength for PCI output clocks
鈥?Programmable output skew between CPU, AGP and PCI
鈥?Maximized electromagnetic interference (EMI)
suppression using Cypress鈥檚 Spread Spectrum
technology
鈥?Low jitter and tightly controlled clock skew
鈥?Two pairs of differential CPU clocks
鈥?Eleven copies of PCI clocks
鈥?Three copies of 66-MHz outputs
鈥?Two copies of 48-MHz outputs
鈥?Three copies of 14.31818-MHz reference clocks
鈥?One RESET output for system recovery
鈥?Power management control support
Key Specifications
CPU outputs cycle-to-cycle jitter: ............................... 250 ps
48-MHz, 3V66, PCI outputs
cycle-to-cycle jitter: ..................................................... 250 ps
CPU 3V66 output skew:.............................................. 200 ps
48-MHz output skew: .................................................. 250 ps
PCI output skew:......................................................... 500 ps
[1]
Block Diagram
VDD_REF
Pin Configuration
REF2
REF1/FS1*
REF0/FS0*
X1
X2
XTAL
OSC
PLL REF FREQ
Divider,
Delay,
and
Phase
Control
Logic
VDD_CPU
CPUT0,CPUC0
2
SDATA
SCLK
SMBus
Logic
CPUT_CS,CPUC_CS
VDD_AGP
AGP0:2
(FS0:4)
3
VDD_PCI
PCI0/SEL24_48#*
PLL 1
PD#
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
5
PCI1:8
PCI9_E
RST#
VDD_48MHz
48MHz/FS3*
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS2/48MHz
*FS3/24_48MHz
GND_48MHz
*FS4/PCI_F
*SEL24_48#/PCI0
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
PCI6
GND_PCI
PCI7
PCI8
PCI9_E
VDD_PCI
RST#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF2
REF_STOP#*
AGP_STOP#*
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT_CS
CPUC_CS
GND_CPU
CPU_STOP#*
PCI_STOP#*
PD#*
VDD_CORE
GND_CORE
SDATA
SCLK
GND_AGP
AGP2
AGP1
AGP0
VDD_AGP
CY28312B-2
PLL2
/2
SEL24_48#*
24_48MHz/FS4*
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Cypress Semiconductor Corporation
Document #: 38-07596 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 1, 2003

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