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CY28158PVCT Datasheet

  • CY28158PVCT

  • Spread Spectrum Timing Solution for Serverworks Chipset

  • 10頁(yè)

  • CYPRESS

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CY28158
Spread Spectrum Timing Solution for Serverworks Chipset
Features
鈥?Maximized EMI suppression using Cypress鈥檚 spread
spectrum technology
鈥?Based on Industry Standard CK133 Pinout with all out-
puts compliant to CK98 specifications
鈥?0.5% downspread outputs deliver up to 10dB lower EMI
鈥?6 skew-controlled copies of CPU output
鈥?6 copies of PCI output (synchronous w/CPU output)
鈥?2 copies of 66 MHz fixed frequency 3.3V clock
鈥?3 copies of 16.67 MHz IOAPIC clock, synchronous to
CPU clock
鈥?1 copy of 48 MHz USB output
鈥?2 copies of 14.31818 MHz reference clock
鈥?Programmable to 133 or 100 MHz operation
鈥?Power management control pins for clock stop and
shut down
鈥?Available in 56-pin SSOP
Key Specifications
Supply Voltages:...................................... V
DD33
= 3.3V 鹵 5%
................................................................ V
DD25
= 2.5V 鹵 5%
CPU Output Jitter: ....................................................<150 ps
CPU Output Skew: ....................................................<175 ps
CPU to 3V66 Output Offset:
CPU to IOAPIC Output Offset
0.0 to1.5 ns
(CPU leads)
1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency.
SEL133/100#
1
0
CPU0:5 (MHz)
133
100
PCI
33.3
33.3
Block Diagram
X1
X2
CPU_STOP#
Pin Configuration
XTAL
OSC
2
REF0:1
STOP
Clock
Logic
6
CPU0:5
SPREAD#
SEL0
SEL1
SEL133/100#
PLL 1
梅2/梅1.5
STOP
Clock
Logic
2
3V66_0:1
1
PCI_F
STOP
Clock
Logic
5
PCI1:5
PWRDWN#
PCI_STOP#
梅2
Power
Down
Logic
3
梅2
IOAPIC0:2
Tristate
Logic
GND_REF
REF0
REF1
VDD_REF
X1
X2
GND_PCI
GND_PCI
PCI_F
VDD_PCI
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
VDD_PCI
PCI5
GND_PCI
GND_3V66
GND_3V66
VDD_3V66
VDD_3V66
GND_3V66
3V66_0
3V66_1
VDD_3V66
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_IOAPIC
IOAPIC2
IOAPIC1
IOAPIC0
GND_IOAPIC
VDD_CPU
CPU5
CPU4
GND_CPU
VDD_CPU
CPU3
CPU2
GND_CPU
VDD_CPU
CPU1
CPU0
GND_CPU
VDDA
GNDA
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SEL1
SEL0
VDD_48MHZ
48MHZ
GND_48MHZ
CY28158
PLL2
1
48MHz
Cypress Semiconductor Corporation
Document #: 38-07039 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised June 25, 2004

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