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CY26503 Datasheet

  • CY26503

  • Clocks and Buffers

  • 12頁(yè)

  • ETC

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CY26503
533-MHz Dual Direct Rambus鈩?Clock Generator
Features
鈥?Differential clock source for 800-MHz and 1066-MHz
Direct Rambus錚?memory subsystem
鈥?Provide synchronization flexibility: the Rambus錚?/div>
channel can also be synchronous to an external system
or processor clock
鈥?Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
鈥?Low-power CMOS design packaged in a 28-pin, 173-mil
TSSOP package
Overview
The Cypress CY26503 provides dual-channel differential
clock signals for a Direct Rambus memory subsystem. It
includes signals to synchronize the Direct Rambus Channel
clock to an external system clock but can also be used in
systems that do not require synchronization of the Rambus
clock.
Key Specifications
Supply Voltage:.................................... V
DD
= 3.3V 鹵 0.165V
Operating Temperature:.................................... 0擄C to +70擄C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: ...................................... V
DD
+ 0.5V
Maximum Input Frequency: .....................................100 MHz
Output Duty Cycle:................................40%/60% worst case
Output Type: ...........................Rambus signaling level (RSL)
Block Diagram
PCLKM0
SYNCLKN0
Pin Configuration
Phase
Alignment
Output
Logic
CLK0
CLK0#
VDDIR
REFCLK
VDD
SYNCLKN0
PCLKM0
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S0
S1
S2
GND
CLK0#
CLK0
VDD
VDD
CLK1
CLK1#
GND
MULT0
MULT1
MULT2
REFCLK
MULT0:2
PLL
GND
SYNCLKN1
PCLKM1
VDD
S0:2
Test
Logic
VDDIPD
STOP#
PWR_DWN#
PCLKM1
SYNCLKN1
Phase
Alignment
Output
Logic
CLK1
CLK1#
PWR_DWN#
STOP#
Cypress Semiconductor Corporation
Document #: 38-07394 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 27, 2002

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