CY26113
One-PLL General Purpose
Clock Generator
Features
鈥?Integrated phase-locked loop
鈥?Low skew, low jitter, high accuracy outputs
鈥?Frequency Select Pin
鈥?3.3V Operation with 2.5V output options
鈥?16-TSSOP
Part Number
CY26113
Outputs
4
Input Frequency
25 MHz
Benefits
Internal PLL with up to 333 MHz internal operation
Meets critical timing requirements in complex system designs
Dynamic frequency selection
Enables application compatibility
Industry standard package saves on board space
Output Frequency Range
4 x 40/80 MHz (selectable)
Logic Block Diagram
XIN
XOUT
P
OSC.
Q
桅
VCO
LCLK2 40/80 MHz
LCLK1 40/80 MHz
Pin Configurations
CY26113
16-pin TSSOP
XIN
VDD
AVDD
OE
AVSS
VSSL
LCLK1
PLL
LCLK3 40/80 MHz
OUTPUT
MULTIPLEXER
AND
DIVIDERS
LCLK4 40/80 MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
NC
NC
VSS
LCLK4
VDDL
FS
LCLK3
FS
LCLK2
OE
VSSL
VDD
AVDD
AVSS
VSS
VDDL
Output
LCLK 1
LCLK 2
LCLK 3
LCLK 4
Pin
7
8
9
12
Default Frequency
40/80 (selectable)
40/80 (selectable)
40/80 (selectable)
40/80 (selectable)
Unit
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07097 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002
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