CY26111
One-PLL General Purpose
Clock Generator
Features
鈥?Integrated phase-locked loop
鈥?Low skew, low jitter, high-accuracy outputs
鈥?3.3V Operation with 2.5V Output Option
鈥?16-TSSOP
Part Number
CY26111
Outputs
4
Input Frequency
25 MHz
Benefits
Internal PLL with up to 333 MHz internal operation
Meets critical timing requirements in complex system designs
Enables application compatibility
Industry standard package saves on board space
Output Frequency Range
3 x 25 MHz, 1 x 125 MHz
Logic Block Diagram
XIN
XOUT
P
OSC.
Q
桅
VCO
OUTPUT
MULTIPLEXER
AND
DIVIDERS
LCLK2 25 MHz
LCLK3 25 MHz
CLK4 125 MHz
LCLK1 25 MHz
Pin Configurations
CY26111
16-pin TSSOP
XIN
VDD
AVDD
OE
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK4
NC
VSS
N/C
VDDL
NC
LCLK3
PLL
OE
VDDL
VSSL
VDD
AVDD
AVSS
VSS
Output
LCLK1
LCLK2
LCLK3
CLK4
Pin
7
8
9
15
Default Frequency
25
25
25
125
Unit
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07095 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 7, 2001
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