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CY26049-5 Datasheet

  • CY26049-5

  • Clocks and Buffers

  • 6頁

  • ETC

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ADVANCE
INFORMATION
CY26049-5
FailSafe鈩?PacketClock鈩?/div>
Global Communications Clock Generator
Features
鈥?Fully integrated phase-locked loop (PLL)
鈥?FailSafe錚?output
鈥?PLL driven by a crystal oscillator that is phase aligned
with external reference
鈥?76.8-MHz output from 19.2-MHz input
鈥?Low-jitter, high-accuracy outputs
鈥?3.3V 鹵 5% operation
鈥?16-lead TSSOP
Benefits
鈥?Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
鈥?When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
鈥?DCXO maintains continuous operation should the input
reference clock fail
鈥?Glitch-free transition simplifies system design
鈥?Works with commonly available, low-cost 19.2-MHz crystal
鈥?Zero-ppm error for all output frequencies
鈥?Compatible across industry standard design platforms
鈥?Industry standard package with 6.4 脳 5.0 mm
2
footprint and
a height profile of just 1.1 mm
Logic Block Diagram
e xte rn a l p u lla b le c rysta l
(1 9 .2 M H z)
X IN
in p u t r e fe re n ce
(1 9 .2 M H z)
IC L K
F A IL S A F E
T M
CONTROL
D IG IT A L
C O N TR O LLE D
C R YSTAL
O S C IL L A T O R
PHASE
LO C K E D
LO O P
CLKA
7 6 .8 M H z
XOUT
O U TPU T
D IV ID E R
SA FE
IC L K d e te cte d
Cypress Semiconductor Corporation
Document #: 38-07485 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised September 8, 2003

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