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CY26049-36 Datasheet

  • CY26049-36

  • Clocks and Buffers

  • 7頁

  • ETC

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PRELIMINARY
CY26049-36
FailSafe鈩?PacketClock鈩?Global
Communications Clock Generator
Features
鈥?Fully integrated phase-locked loop (PLL)
Benefits
鈥?Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
鈥?When reference is in range, SAFE pin is driven high.
鈥?When reference is off, DCXO maintains clock outputs. SAFE
pin is low.
鈥?DCXO maintains continuous operation should the input
reference clock fail
鈥?Glitch-free transition simplifies system design
鈥?Selectable output clock rates include T1/DS1, E1, T3/DS3,
E3, and OC-3.
鈥?Works with commonly available, low-cost 18.432-MHz
crystal
鈥?Zero-ppm error for all output frequencies
鈥?Performance guaranteed for applications that require an
extended temperature range
鈥?Compatible across industry standard design platforms
鈥?Industry standard package with 6.4 x 5.0 mm
2
footprint and
a height profile of just 1.1 mm
鈥?FailSafe錚?output
鈥?PLL driven by a crystal oscillator that is phase aligned
with external reference
鈥?Output frequencies selectable and/or programmed to
standard communication frequencies
鈥?Low-jitter, high-accuracy outputs
鈥?Commercial and Industrial operation
鈥?3.3V 鹵 5% operation
鈥?16-lead TSSOP
Logic Block Diagram
external pullable crystal
(18.432 MHz)
XIN
Input reference
(typical 8 kHz)
ICLK
TM
FAILSAFE
CONTROL
XOUT
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
PHASE
LOCKED
LOOP
CLK
OUTPUT
DIVIDERS
CLK/2
FS[3:0]
frequency select
8K
SAFE
High=ICLK detected
Cypress Semiconductor Corporation
Document #: 38-07415 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised July 3, 2003

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