CY25245
Frequency-multiplying, Peak-reducing
EMI Solution
Features
鈥?Cypress PREMIS鈩?SMARTSPREAD鈩?family offering
鈥?Generates an electromagnetic interference (EMI)
optimized clocking signal at the output
鈥?Selectable output frequency range
鈥?Single 1.25%, 2.5%, 5%, or 10% down or center spread
output
鈥?Integrated loop filter components
鈥?Operates with a 3.3 or 5V supply
鈥?Low power CMOS design
鈥?Available in 20-pin Small Shrunk Outline Package
(SSOP)
Key Specifications
Supply voltages: .......................................V
DD
= 3.3V 鹵 0.3V
or V
DD
= 5V 鹵 10%
Frequency range:............................ 13 MHz
鈮?/div>
F
in
鈮?/div>
166 MHz
Cycle-to-cycle jitter: ......................................... 250 ps (max)
Output duty cycle: ................................ 40/60% (worst case)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
[1, 2]
SSOP
X1
XTAL
Input
X2
CY25245
SDATA
SCLK
Serial Interface
Spread Spectrum
Output
(EMI suppressed)
X1
X2
AVDD
MW0^
SDATA
OR1^
SCLK
GND
OR2*
SSON#^
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
VDD
MW2^
CY25245
3.3V or 5.0V
Oscillator or
Reference Input
X1
CY25245
SDATA
Serial Interface
SCLK
Spread Spectrum
Output
(EMI suppressed)
Notes:
1. Pins marked with ^ are internal pull-down resistors with weak 250 k鈩?
2. Pins marked with * are internal pull-up resistors with weak 80 k鈩?
Cypress Semiconductor Corporation
Document #: 38-07124 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 7, 2003
CY25245相關(guān)型號(hào)PDF文件下載
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