CY24712 Datasheet

IC型號(hào)：
CY24712
PDF描述：
Clocks and Buffers
文件大?。?/label>
91.27KB
PDF頁數(shù)：
5頁
芯片廠家：
ETC

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CY24712

MediaClock鈩?/div>

Set-top Box Clock Generator with VCXO

Features

鈥?Integrated phase-locked loop (PLL)

鈥?Low-jitter, high-accuracy outputs

鈥?VCXO with analog adjust

鈥?3.3V Operation

鈥?8-pin SOIC

Part Number

CY24712

Outputs

Input Frequency Range

27-MHz pullable crystal input

per Cypress specification

Benefits

High-performance PLL tailored for Set Top Box applications

Meets critical timing requirements in complex system designs

Large 鹵150-ppm range, better linearity

Meet industry standard voltage platforms

Industry standard packaging saves on board space

Output Frequencies

11.0592 MHz, 13.5 MHz, 27 MHz

Logic Block Diagram

CLK_C 27 MHz

27 XIN

XOUT

OSC

桅

VCO

OUTPUT

DIVIDERS

CLK_A 11.0592 MHz

VCXO

PLL

CLK_B 13.5 MHz

VDD

VSS

Pin Configuration

CY24712

8-pin SOIC

XIN

VDD

VCXO

VSS

XOUT

CLK_C

CLK_A

CLK_B

Cypress Semiconductor Corporation

Document #: 38-07319 Rev. *B

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

鈥?/div>

CA 95134 鈥?408-943-2600

Revised December 14, 2002

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