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CY24239PVC Datasheet

  • CY24239PVC

  • CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC

  • 15頁(yè)

  • ETC

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39
CY24239
Spread Spectrum Frequency Timing Generator
Features
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?鈥?.2% and 鈥?.4% Spread Spectrum support
鈥?Three copies of CPU output
鈥?Seven copies of PCI output
鈥?One 48-MHz output for USB / One 24-MHz for SIO
鈥?Two buffered reference outputs
鈥?Two IOAPIC outputs
鈥?Seventeen SDRAM outputs provide support for
4 DIMMs
鈥?SMBus interface for programming
鈥?Power management control inputs
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
CPU1:2
FS3 FS2 FS1 FS0
(MHz)
1
1
1
1
91.66
1
1
1
0
75.0
1
1
0
1
100.0
1
1
0
0
83.3
1
0
1
1
66.6
1
0
1
0
105.0
1
0
0
1
110.0
1
0
0
0
133.3
0
1
1
1
91.66
0
1
1
0
75.0
0
1
0
1
100.0
0
1
0
0
83.3
0
0
1
1
91.66
0
0
1
0
75.0
0
0
0
1
100.0
0
0
0
0
83.3
PCI_F,
PCI0:5
(MHz)
30.5
25.0
33.3
27.76
33.3
26.3
27.5
33.3
30.5
25.0
33.3
27.76
30.5
25.0
33.3
27.76
Spread
Spec-
trum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
鈥?.2%
鈥?.2%
鈥?.2%
鈥?.2%
鈥?.4%
鈥?.4%
鈥?.4%
鈥?.4%
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 350 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:16 Delay: ..........................3.7 ns typ.
V
DDQ3
: .................................................................... 3.3V鹵5%
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Block Diagram
VDDQ3
REF0/(PCI_STOP#)
X1
X2
XTAL
OSC
REF1/FS2
PLL Ref Freq
Stop
Clock
Control
Pin Configuration
[1]
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ3
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ3
CPU2
GND
CLK_STOP#
SDRAM16
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
I/O Pin
Control
CLK_STOP#
VDDQ3
IOAPIC_F
IOAPIC0
VDDQ3
CPU_F
CY24239
PLL 1
梅2,3,4
Stop
Clock
Control
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
Stop
Clock
Control
SDATA
SCLK
SMBus
Logic
PCI4
PCI5
VDDQ3
PLL2
Stop
Clock
Control
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:16
17
SDRAMIN
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07038 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised May 18, 2001

CY24239PVC 產(chǎn)品屬性

  • Cypress Semiconductor

  • 鎖相環(huán)路 (PLL)

  • PLL Clock Generator

  • 2

  • 24 MHz to 133.3 MHz

  • 3.465 V

  • 3.135 V

  • + 70 C

  • 0 C

  • SSOP-56

  • SMD/SMT

  • 3.3 V

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