PRELIMINARY
CY24206
MediaClock鈩?DTV, STB Clock Generator
Features
鈥?Integrated phase-locked loop
鈥?Low-jitter, high-accuracy outputs
鈥?3.3V operation
Benefits
Internal PLL with up to 400-MHz internal operation
Meets critical timing requirements in complex system designs
Enables application compatibility
Part Number
CY24206-1
Outputs
3
Input Frequency
27 MHz
Output Frequency Range
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
CY24206-2
4
27 MHz
CY24206-3
4
27 MHz
CY24206-4
4
27 MHz
Logic Block Diagram
XIN
XOUT
P
OSC.
Q
桅
VCO
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLK1
CLK2
REFCLK
FS0
FS1
FS2
OE
CLK3 (-2, -3,-4)
PLL
Pin Configurations
CY24206-1
16-pin TSSOP
XIN
VDD
AVDD
OE
AVSS
VSSL
CLK1
CLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS2
FS1
VSS
N/C
VDDL
VDDL
VDD
AVDD
AVSS
VSS
VSSL
CY24206-2,3,4
16-pin TSSOP
XOUT
XIN
VDD
AVDD
OE
AVSS
VSSL
CLK1
CLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
FS2
FS1
VSS
CLK3
VDDL
FS0
REFCLK
FS0
REFCLK
Cypress Semiconductor Corporation
Document #: 38-07451 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 27, 2003
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