PRELIMINARY
CY24202
27-MHz Clock Generator with
Serial Programming Interface
Features
鈥?Integrated phase-locked loop
鈥?Low jitter, high accuracy outputs
鈥?Serial Programming Interface (SPI)
鈥?3.3V Operation
Part Number
CY24202
Outputs
2
Input Frequency Range
13.5-MHz pullable crystal input per
Cypress Specification
Benefits
High-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Dynamic Digital VCXO control
Enables application compatibility in low power systems
Output Frequencies
2 copies of 27 MHz
Logic Block Diagram
13.5 XIN
OSC
XOUT
Q
桅
VCO
P
CLK2
CLK1
OUTPUT
DIVIDERS
PLL
Digital VCXO
Serial
Programming
Interface
SCLK
SDAT
VDD
VSS
Pin Configuration
CY24202
8-pin SOIC
XIN
VDD
SDAT
VSS
1
2
3
4
8
7
6
5
XOUT
CLK2
CLK1
SCLK
Cypress Semiconductor Corporation
Document #: 38-07198 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002
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