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Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Advance Features
鈥?Lower drive strength settings (CY241V08-04, -06)
Benefits
鈥?Electromagnetic interference (EMI) reduction for standards
compliance
Benefits
鈥?Highest-performance PLL tailored for multimedia applica-
tions
鈥?Meets critical timing requirements in complex system
designs
鈥?Application compatibility for a wide variety of designs
Frequency Table
Part
Number
CY241V08-01
CY241V08-04
CY241V08-05
CY241V08-06
Outputs
1
1
1
1
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
Pinout compatible with MK3727
Same as CY241V08-01 except
lower drive strength settings
Mimics MK3727 nonlinear
VCXO Control Curve
Same as CY241V08-05 except
lower drive strength settings
13.5-MHz pullable crystal input One copy of 27 MHz linear
per Cypress specification
13.5-MHz pullable crystal input One copy of 27 MHz linear
per Cypress specification
13.5-MHz pullable crystal input One copy of 27 MHz nonlinear
per Cypress specification
13.5-MHz pullable crystal input One copy of 27 MHz nonlinear
per Cypress specification
Block Diagram
13.5 XIN
OSC
XOUT
PLL
OUTPUT
DIVIDER
27 MHz
VCXO
VDD
VSS
Pin Configuration
CY241V08-01,-04,-05,-06
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
Cypress Semiconductor Corporation
Document #: 38-07520 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised July 28, 2003
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