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Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Benefits
鈥?Highest-performance PLL tailored for multimedia applica-
tions
鈥?Meets critical timing requirements in complex system
designs
鈥?Application compatibility for a wide variety of designs
Frequency Table
Part Number Outputs
CY241V08-41
1
Input Frequency Range
VCXO Control
Output Frequencies
Curve
Other Features
Pinout compatible with MK3741
27-MHz pullable crystal input One copy of 27MHz
linear
per Cypress specification
One copy of 83.33MHz
(non-pullable)
Block Diagram
54 REF
PLL
OSC
OUTPUT
DIVIDER
83.33MHz
27 XIN
XOUT
XBUF/27MHz
VCXO
VDD
VSS
Pin Configuration
CY241V08-41
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
REF
83.33 MHz
XBUF/27 MHz
Cypress Semiconductor Corporation
Document #: 38-07570 Rev. **
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised September 8, 2003
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