MediaClock鈩?/div>
Graphics Clock Generator
Features
鈥?Integrated phase-locked loop (PLL)
鈥?Low-jitter, high-accuracy output
鈥?3.3V operation with 2.5V/1.68V output
鈥?Ultra-linear crystal capacitors
Part Number
CY24141-3
Outputs
2
Input Frequency Range
18.432 MHz
Benefits
High-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Enables application compatibility
Ensures 0PPM Accuracy
Output Frequencies
18.432 MHz, 53.94605395 MHz/54 MHz (selectable)
Logic Block Diagram
CLK_A 18.432 MHz
XIN
OSC
XOUT
Q
桅
VCO
P
OUTPUT
DIVIDER
CLK_B (selectable)
PLL
FS
AVDD VDDL
AVSS
VSSL
VDD
VSS
Pin Configurations
CY24141ZC-3
16-pin TSSOP
XIN
VDD
AVDD
FS
AVSS
VSSL
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK_A
N/C
VSS
N/C
VDDL
N/C
CLK_B
CY24141 Frequency Select Table
Frequency Select
1
0
PPM
鈥?.000073
0
CLK_B
53.94605395
54
Unit
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07324 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?408-943-2600
Revised April 4, 2002
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