CY2412
MPEG Clock Generator with VCXO
Features
鈥?Integrated phase-locked loop (PLL)
鈥?Low-jitter, high-accuracy outputs
鈥?VCXO with analog adjust
鈥?3.3V operation
Part Number
CY2412
CY2412-2
Outputs
3
3
Input Frequency Range
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large 鹵150-ppm range, better linearity
Enables application compatibility
Output Frequencies
13.5-MHz pullable crystal input per Two 27-MHz outputs, one 54-MHz output (3.3V)
Cypress specification
13.5-MHz pullable crystal input per 27 MHz, 13.5 MHz, 54 MHz (3.3V)
Cypress specification
Logic Block Diagram
Pin Configuration
CY2412,-2
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
CLKC
CLKB
CLKA
CLKC
13.5 XIN
OSC
XOUT
Q
桅
VCO
P
OUTPUT
DIVIDERS
CLKB
CLKA
VCXO
PLL
VDD
VSS
Cypress Semiconductor Corporation
Document #: 38-07227 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised March 13, 2002
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