MediaClock鈩?/div>
MPEG Clock Generator with VCXO
Features
鈥?Integrated phase-locked loop (PLL)
鈥?Low-jitter, high-accuracy outputs
鈥?VCXO with analog adjust
鈥?3.3V operation
Part Number
CY2411-1
Outputs
1
Input Frequency Range
13.5-MHz Pullable Crystal per
Cypress Specification
Output Frequencies
1 copy of 54 MHz (3.3V)
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large 鹵 150 ppm range, better linearity
Logic Block Diagram
13.5 XIN
OSC
XOUT
Q
桅
VCO
P
VCXO
OUTPUT
DIVIDER
54 MHz
Pin Configuration
CY2411
8-pin SOIC
XIN
AVDD
VCXO
AVSS
1
2
3
4
8
7
6
5
XOUT
VSS
54 MHz
VDD
PLL
AVDD VDD
AVSS
VSS
Pin Summary
Pin Name
A
VDD
V
DD
AV
SS
V
SS
X
IN
V
CXO
X
OUT
[1]
Pin Number
2
5
4
7
1
3
8
6
Pin Description
Analog Voltage Supply
Output Voltage Supply
Analog Ground
Output Ground
Reference Crystal Input
Analog Control for V
CXO
Reference Crystal Output
54-MHz clock output
54 MHz
Note:
1. Float X
OUT
if X
IN
is externally driven.
Cypress Semiconductor Corporation
Document #: 38-07193 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002
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