MediaClock鈩?/div>
Mini Disc Clock Generator
Features
鈥?Integrated phase-locked loop (PLL)
鈥?Low-jitter, high-accuracy outputs
鈥?3.3V operation
鈥?8-pin SOIC package
Part Number
CY24115-1
CY24115-2
Outputs
1
1
Input Frequency Range
1 MHz鈥?0 MHz
1 MHz鈥?0 MHz
Benefits
High-performance PLL tailored for mini disc applications
Meets critical timing requirements in complex system designs
Enables application compatibility
Industry standard package saves on board space
Output Frequencies
45.1584 MHz/90.3168 MHz (selectable)
90.3168 MHz/180.6336 MHz (selectable)
Logic Block Diagram
XIN
XOUT
OSC
Q
桅
VCO
P
OUTPUT
DIVIDERS
CLKA
PLL
FS0
FS1
CLKSEL
FREQUENCY
TABLE
VDD
VSS
Table 1. CLKSEL Function CY24115-1
CLKSEL
CLKA
45.1584
Unit
MHz
PPM Error
0
0
0
Pin Configurations
CY24115
8-pin SOIC
XIN
VDD
CLKSEL
VSS
1
2
3
4
8
7
6
5
XOUT
FS1
FS0
CLKA
1
90.3168
MHz
Table 2. CLKSEL Function, CY24115-2
CLKSEL
0
CLKA
90.3168
Unit
MHz
PPM Error
0
1
180.6336
MHz
0
Table 3. Input Frequency Function, CY24115-1 and CY24115-2
FS1
0
0
1
1
FS0
0
1
0
1
Xtal Input
2.8224
5.6448
11.2896
22.5792
Unit
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07275 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002
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