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CY23FS08OC Datasheet

  • CY23FS08OC

  • Failsafe 2.5V/ 3.3V Zero Delay Buffer

  • 239.78KB

  • 12頁

  • CYPRESS

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CY23FS08
Failsafe鈩?2.5V/ 3.3V Zero Delay Buffer
Features
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Internal DCXO for continuous glitch-free operation
Zero input-output propagation delay
Low jitter (< 35 ps RMS) outputs
Low output-output skew (< 200 ps)
1 MHz鈥?00 MHz reference input
Supports industry standard input crystals
200 MHz (commercial), 166 MHz (industrial) outputs
5V-tolerant inputs
Phase-locked loop (PLL) Bypass Mode
Dual Reference Inputs
28-pin SSOP
Split 2.5V or 3.3V output power supplies
3.3V core power supply
Industrial temperature available
Functional Description
The CY23FS08 is a FailSafe
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Zero Delay Buffer with two
reference clock inputs and eight phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
Continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by four select lines:
S[4:1]. please see
Table 1.
The CY23FS08 has three split
power supplies; one for core, another for Bank A outputs and
the third for Bank B outputs. Each output power supply, except
VDDC can be connected to either 2.5V or 3.3V. VDDC is the
power supply pin for internal circuits and must be connected
to 3.3V.
Block Diagram
Pin Configuration
XIN XOUT
REFSEL
DCXO
REF1
REF2
FBK
Failsafe
TM
Block
PLL
REF1
REF2
VSSB
CLKB1
4
4
CLKA[1:4]
CLKB[1:4]
CLKB2
S2
S3
VDDB
VSSB
CLKB3
Decoder
FAIL# /SAFE
S[4:1]
4
CLKB4
VDDB
VDDC
XIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CY23FS08
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REFSEL
FBK
VSSA
CLKA1
CLKA2
S1
S4
VDDA
VSSA
CLKA3
CLKA4
VDDA
FAIL#/SAFE
XOUT
28 pin SSOP
Cypress Semiconductor Corporation
Document #: 38-07518 Rev. *A
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised May 12, 2004

CY23FS08OC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Stepper System Controller
    ETC
  • 英文版
    Stepper System Controller
    ETC [ETC]
  • 英文版
    Stepper System Controller
    ETC
  • 英文版
    Stepper System Controller
    ETC [ETC]
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS
  • 英文版
    Phase-Aligned Clock Multiplier
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  • 英文版
    Frequency Multiplier and Zero Delay Buffer
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  • 英文版
    Frequency Multiplier and Zero Delay Buffer
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  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...

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