35ps typ. output-to-output skew (same freq)
鈥?110 ps typ. cycle-cycle jitter (same freq)
鈥?Spread Aware錚?/div>
鈥?28-pin SSOP
鈥?3.3V operation
鈥?Industrial temperature available
Functional Description
The CY23FP12 is a high-performance fully field-program-
mable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using
high-performance ASICs and microprocessors.
The CY23FP12 is fully programmable via volume or prototype
programmers enabling the user to define an appli-
cation-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2,
and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12 also features a proprietary auto-power-down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50
碌A
of current draw.
The CY23FP12 provides twelve outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5V or a 3.3V rail.
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/deasserted.
Block Diagram
VDDC
VDDA
CLKA0
Lock Detect
Pin Configuration
SSOP
Top View
REF2
REF1
CLKB0
CLKB1
V
SSB
CLKB2
CLKB3
V
DDB
V
SSB
CLKB4
CLKB5
V
DDB
V
DDC
S2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKA1
CLKA2
CLKA3
REFSEL
FBK
CLKA0
CLKA1
V
SSA
CLKA2
CLKA3
V
DDA
V
SSA
CLKA4
CLKA5
V
DDA
V
SSC
S1
REFSEL
REF1
REF2
FBK
梅
M
梅
N
100 to
400MHz
PLL
梅
1
梅
2
梅
3
梅
4
梅
X
CLKA4
CLKA5
VSSA
VDDB
CLKB0
CLKB1
CLKB2
CLKB3
Test Logic
S[2:1]
VSSC
Function
Selection
CLKB4
CLKB5
VSSB
Cypress Semiconductor Corporation
Document #: 38-07246 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 13, 2004
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