CY2305 and CY2309 as PCI and SDRAM Buffers
Introduction to Cypress Zero Delay Buffers
What is a Zero Delay Buffer?
A zero delay buffer is a device that can fan out 1 clock signal
into multiple clock signals with zero delay and very low skew
between the outputs. This device is well suited as a buffer for
PCI or SDRAM due to its zero input to output delay and very
low output to output skew.
A simplified diagram of the CY2308 zero delay buffer is shown
in
Figure 1.
The CY2308 is built using a PLL that uses a ref-
erence input and a feedback input. The feedback loop is
closed by driving the feedback input (FBK) from one of the
outputs. The phase detector in the PLL adjusts the output
frequency of the VCO so that the two inputs have no phase
difference. Since an output is one of the inputs to the PLL,
zero phase difference is maintained from REF to the output
driving FBK. Now if all outputs are uniformly loaded, zero
phase difference will be maintained from REF to all outputs.
This is a simple zero delay buffer. Introducing additional de-
vices (e.g., dividers) between the output and FBK can give
rise to some innovative applications for the PLL, and for fur-
ther information on these refer to the Cypress Application
Note
鈥淐Y2308 Zero Delay Buffer鈥?
Since many buffering ap-
plications require only a simple closure of the feedback loop,
Cypress has designed zero delay buffers with Internal Feed-
back Loops: the CY2305 and CY2309.
What are the CY2305 and CY2309?
Cypress has designed zero delay buffers especially suited for
use with PCI or SDRAM buffering. The CY2305 and CY2309
have been designed with the feedback path integrated for
simpler system design. A simplified block diagram of the
CY2309 zero delay buffer is shown
Figure 2.
This zero delay
buffer uses a input/output pad on CLKOUT so that the feed-
back signal can be sensed directly from the output itself.
Drive Capability
The CY2305 and CY2309 have high drive outputs designed
to meet the JEDEC SDRAM specifications of 30 pF capaci-
tance on each DIMM clock input.
Since the typical CMOS input is 7 pF and the CY2305/09 are
designed to drive up to 30 pF; this means that up to 4 CMOS
inputs can be driven from a single output of a CY2305/09.
However the output loading on the CY2305/09 must be equal
on all outputs to maintain zero delay from the input.
Power Down
The CY2305 and CY2309 have a unique power-down mode:
if the input reference is stopped, the part automatically enters
a shutdown state, shutting down the PLL and three-stating the
outputs. When the part is in shutdown mode it draws less than
50
碌A(chǔ),
and can come out of shutdown mode with the PLL
locked in less than 1 ms. This power down mode can also be
entered by three-stating the input reference driver and allow-
ing the internal pull-down to pull the input LOW (the input
does not have to go LOW, it only has to stop).
5 Volt to 3.3 Volt Level Shifting
The CY2305 and CY2309 can act as a 5-volt to 3.3-volt level
shifter. The reference input pad is 5-volt signal-compatible.
Since many system components still operate at 5 volts, this
feature provides the capability to generate multiple 3.3-volt
clocks from a single 5-volt reference clock. This 5-volt sig-
nal-compatibility is only available on the reference pad; the
other input pads on the CY2309 are not 5-volt compatible.
REF
Phase
Loop
Detector
Filter
VCO
MUX
FBK
CLKA1
CLKA2
CLKA3
REF
Phase
Loop
Detector
Filter VCO
CLKOUT
MUX
CLKA1
CLKA2
CLKA3
CLKA4
PLL
PLL
S2
S1
CLKA4
Select Input
Decoding
CLKB1
CLKB2
CLKB3
CLKB4
S2
S1
Select Input
Decoding
CLKB1
CLKB2
CLKB3
CLKB4
Figure 1. Simplified Block Diagram of CY2308
Figure 2. Simplified Block Diagram of CY2309
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
March 25, 1997 鈥?Revised July 29, 1997
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