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CY2303 Datasheet

  • CY2303

  • Clocks and Buffers

  • 101.16KB

  • 7頁

  • ETC

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3
CY2303
Phase-Aligned Clock Multiplier
Features
鈥?3-multiplier configuration
鈥?Single phase-locked loop architecture
鈥?Phase Alignment
鈥?Low jitter, high accuracy outputs
鈥?Output enable pin
鈥?3.3V operation
鈥?5V Tolerant input
鈥?Sophisticated internal loop filter
鈥?8-pin 150-mil SOIC package
鈥?Commercial and Industrial Temperature available
1x, 2x, 4x Ref
10 MHz to 166.67 MHz operating range (reference input from
10 MHz to 41.67 MHz)
All outputs will have a consistent phase relationship with each
other and the reference input
Meets critical timing requirements
Enables design flexibility and lower power consumption
Supports industry standard design platforms
Allows flexibility on Reference input
Alleviates the need for external components
Industry standard packaging saves on board space
Suitable for wide spectrum of applications
Benefits
Selector Guide
Part Number
CY2303SC
CY2303SI
Outputs
3
3
Input Frequency Range
10 MHz鈥?1.67 MHz
10 MHz鈥?1.67 MHz
Output Frequency Range
10 MHz鈥?66.67 MHz
10 MHz鈥?66.67 MHz
Specifics
Commercial Temperature
Industrial Temperature
Functional Description
The CY2303 is a 3 output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows user to obtain 1x, 2x, and 4x Ref output fre-
quencies on respective output pins.
The CY2303 has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The PLL feedback is internally
connected to the REF output. The input-to-output skew is
guaranteed to be less than
鹵200
ps, and output-to-output skew
is guaranteed to be less than 200 ps.
Multiple CY2303 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2303 is available in commercial and industrial temper-
ature ranges.
Block Diagram
FBK
Pin Configuration
8-pin SOIC
Top View
x1
PLL
x2
REFx2
REF
REFIN
REF
GND
REFIN
N/C
1
2
3
4
8
7
6
5
OE
V
DD
REFx4
REFx2
x4
OE
REFx4
Cypress Semiconductor Corporation
Document #: 38-07249 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 7, 2002

CY2303相關(guān)型號PDF文件下載

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    版本
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  • 英文版
    Stepper System Controller
    ETC
  • 英文版
    Stepper System Controller
    ETC [ETC]
  • 英文版
    Stepper System Controller
    ETC
  • 英文版
    Stepper System Controller
    ETC [ETC]
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS [C...
  • 英文版
    Frequency Multiplier and Zero Delay Buffer
    CYPRESS
  • 英文版
    Frequency Multiplier and Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...

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