鈮?/div>
175 ps between CPU clocks
Early PCI clock leads PCI by 1鈥? ns (-2 option)
DIV4 allows dynamic shifting of CPU and PCI clocks
from the default frequency to default/4 (-2 option)
Factory-EPROM programmable output drive and slew
rate for EMI customization
Available in space-saving 28-pin SSOP package
The CY2285 possesses power-down, CPU stop, and PCI stop
pins for power management control. The signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
The CY2285-2 features an early PCI clock which leads the
other PCI clocks by 1鈥? ns. The CY2285-2 also features a
DIV4 pin which allows for dynamic shifting of CPU and PCI
clocks from the default frequency to the default/4.
CY2285 Selector Guide
Clock Outputs
CPU (66,
100 MHz)
PCI (CPU/2,
CPU/3 MHz)
Ref. (14.318 MHz)
USB (48 MHz)
USB/IO (48
MHz/24 MHz se-
lectable)
CPU-PCI delay
EPCI-PCI delay
Spread Spectrum
CY2285-1
2
6
[1]
2
1
1
CY2285-2
2
7
[1, 2]
2
1
N/A
CY2285-3
2
6
[1]
1
1
1
Functional Description
The CY2285 is a clock synthesizer/driver for Pentium II, or
other similar processor-based mobile PCs requiring up to
100-MHz support. The CY2285 outputs two CPU clocks at
2.5V. There are six PCI clocks, running at one-half or one-third
the CPU clock frequency of 66.6 MHz and 100 MHz respec-
tively. One of the PCI clocks is free-running. Additionally, the
part outputs two 3.3V reference clocks at 14.318 MHz.
The CY2285 provides incorporates the Intel廬-defined spread
spectrum features. It provides a 鈥?.6% downspread on the
CPU and PCI clocks, which can help reduce EMI in certain
high-speed systems.
1.5鈥?.0 ns
N/A
1.5鈥?.0 ns
1.0鈥?.0 ns
1.5鈥?.0 ns
N/A
鈥?.6%
鈥?.6%
鈥?.6%
Downspread Downspread Downspread
Notes:
1. One free-running PCI clock.
2. One early PCI clock.
SPREAD (-2,-3 option)
REF0/SPREAD
REF0 (-2 option)
Logic Block Diagram
DIV4
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
/4
STOP
LOGIC
Divider
REF1/SEL48
REF1 (-2,-3 option)
V
DDREF
CPUCLK [0鈥?]
V
DDCPU
EPCICLK (-2 option)
EPROM
Delay
STOP
LOGIC
PWR_DWN
V
DDPCI
PCICLK [1-5]
V
DDPCI
PCICLK_F
V
DDPCI
CPU_STOP
PCI_STOP
SYS
PLL
USBCLK
V
DD48
USB_IOCLK/TS (-1 option)
USBCLK/SEL100/66 (-2 option)
V
DD48
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
May 18, 2000
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