CY2212
Direct Rambus鈩?Clock Generator (Lite)
Features
鈥?Direct Rambus鈩?Clock Support
鈥?High-speed Clock Support
鈥?Input Select Option
鈥?Crystal Oscillator Divider Output
鈥?Output edge-rate control
鈥?16-pin TSSOP
Benefits
One pair of differential output drivers
400-MHz maximum, 300-MHz minimum output frequency
PLL multiplier select
LCLK = XTAL/2, not driven by phase-locked loop (PLL)
Minimize EMI
Space-saving, low-cost package
Logic Block Diagram
CLK
CLKB
XIN
XOUT
Xtal
Oscillator
PLL
xM
S
/2
LCLK
Xtal Value = 18.75 MHz
Pin Configuration
16-pin TSSOP
TOP VIEW
VDDP
VSSP
XOUT
XIN
VDDL
LCLK
VSSL
NC
1
2
3
4
5
6
7
8
16
15
14
S
VDD
VSS
CLK
CLKB
VSS
VDD
NC
CY2212
13
12
11
10
9
Frequency Select Table
S
0
1
M (PLL Multiplier)
16
64/3
CLK,CLKB
300 MHz
400 MHz
LCLK
9.375 MHz
9.375 MHz
Cypress Semiconductor Corporation
Document #: 38-07466 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 9, 2002
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