鈥?/div>
Eight channel 10 bit A / D converter
Approved
ISO
interface , slew rate limitation,
bidirectional serial interface driver according ISO 9141
Two small signal stages with diagnostics
SPI interface
All I / O 鈥?ports designed for 2.5 V to 3.6 V logic level
Package : LQFP32
PIN DESCRIPTION
Pin Name
AREF GNDA VDD5A
AN_IN0..7
RAM
AD Converter
8 Channel
Reset
Function
Receiver output driver ISO 9141
Transmitter input driver ISO 9141
Input/output driver ISO 9141
UB-Reference for the ISO 9141 receiver
Output small signal stage 1
Output small signal stage 2
Input small signal stage 1
Input small signal stage 2
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5 ( only half sample rate of the
others channels )
Analog input 6
Analog input 7
CLK-input for the
A-to-D
Converter
( Necessary to enable the CY100 )
Interrupt-Output for the A-to-D Converter
SPI slave-select signal
Slave-Out signal ( SPI data output )
Slave-In signal ( SPI data input )
SPI serial clock input
Analog reference voltage for the ADC
Analog supply voltage 5 V
Analog ground
UBat
Pin
for
ESD
protection
5 V - digital supply
3.3 V / 2.5 V - supply for IO
Digital-ground mainly for 鈥檕n chip鈥?digital
modules
Digital-ground mainly for 鈥檕n chip鈥?power
modules like ISO, KSA and SPI
Reset-input
not used -> to be connected to ground
CLK
VDD5
INT
+ Logic
SI
SO
SPI-Interface
SPI
(for diagnosis) Reset
SCK
SS
16
15
14
13
9
10
8
7
32
31
30
29
28
27
26
25
22
23
17
19
18
20
1
2
3
12
6
21
5
11
4
24
RX
TX
RT
UB_REF
A1
A2
E1
E2
AN_IN0
AN_IN1
AN_IN2
AN_IN3
AN_IN4
AN_IN5
AN_IN6
AN_IN7
CLK
INT
SS
SO
SI
SCK
AREF
VDD5A
GNDA
UBat
VDD5
VDDIO
GND1
GND2
RST
TST
E1
small signal
stages
-1
Reset
ISO-Interface
UBREF
RX
E2
A2
A1
2x
ISO9141
-1
TX
RT
Reset
RST
TST
GNDL
GND2
VDDIO
UBat
1
漏1/2004 All rights reserved by Robert Bosch GmbH including the right to file industrial property rights
Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution.
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