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PROCESS

Power Transistor

CP709

Central

TM

PNP - Low Saturation Transistor Chip

Semiconductor Corp.

PROCESS DETAILS

Process

Die Size

Die Thickness

Base Bonding Pad Area

Emitter Bonding Pad Area

Top Side Metalization

Back Side Metalization

GEOMETRY

GROSS DIE PER 4 INCH WAFER

6,670

PRINCIPAL DEVICE TYPES

CMPT7090L

CXT7090L

CZT7090L

CMXT7090L

EPITAXIAL PLANAR

41.3 x 41.3 MILS

9.0 MILS

9.5 x 9.2 MILS

12.8 x 10.2 MILS

Al - 30,000脜

Au - 18,000脜

145 Adams Avenue

Hauppauge, NY 11788 USA

Tel: (631) 435-1110

Fax: (631) 435-1824

www.centralsemi.com

R2 (12- September 2003)

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