CXL5514M/P
CMOS-CCD 1H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
The CXL5514M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL signals including
the external lowpass filter.
Features
鈥?/div>
Single 5V power supply
鈥?/div>
Low power consumption
鈥?/div>
Built-in peripheral circuit
鈥?/div>
Built-in tripling PLL circuit
鈥?/div>
Sync tip clamp mode
Absolute Maximum Ratings
(Ta = 25擄C)
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Supply voltage
V
DD
+6
鈥?/div>
Operating temperature Topr
鈥?0 to +60
鈥?/div>
Storage temperature Tstg
鈥?5 to +150
鈥?/div>
Allowable power dissipation
P
D
CXL5514M 350
CXL5514P 480
Recommended Operating Range
(Ta = 25擄C)
V
DD
5V 鹵 5%
Recommended Clock Conditions
(Ta = 25擄C)
鈥?/div>
Input clock amplitude
V
CLK
0.2 to 1.0Vp-p (0.4Vp-p Typ.)
鈥?/div>
Clock frequency
f
CLK
4.433619MHz
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Input clock waveform Sine wave
Block Diagram and Pin Configuration
(Top View)
V
DD
8
VCO OUT
7
VCO IN
6
CLK
5
CXL5514M
8 pin SOP (Plastic)
CXL5514P
8 pin DIP (Plastic)
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 575mVp-p (Max.)
(at internal clamp condition)
V
擄C
擄C
Functions
鈥?/div>
848-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
Auto-bias circuit
鈥?/div>
Sync tip clamp circuit
鈥?/div>
Sample and hold circuit
鈥?/div>
Tripling PLL circuit
鈥?/div>
Inverted output
Structure
CMOS-CCD
mW
mW
PLL
Auto-bias circuit
Timing circuit
Clamp circuit
CCD
(848 bit)
Output circuit
(S/H 1 bit)
Clock driver
Bias circuit A
Bias circuit B
1
IN
2
AB
3
OUT
4
V
SS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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英文版
CMOS-CCD 1H Delay Line for PAL
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英文版
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英文版
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英文版
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英文版
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英文版
CMOS-CCD 1H Delay Line for NTSC
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英文版
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