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CXL5513P Datasheet

  • CXL5513P

  • CMOS-CCD 1H Delay Line for NTSC

  • 9頁(yè)

  • SONY   SONY

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CXL5513M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5513M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1 H delay time for NTSC chroma signals
including the external lowpass filter.
Features
鈥?/div>
Single 5 V power supply
鈥?/div>
Low power consumption
鈥?/div>
Built-in peripheral circuit
鈥?/div>
Built-in tripling PLL circuit
鈥?/div>
Center bias mode
Absolute Maximum Ratings
(Ta=25 擄C)
鈥?/div>
Supply voltage
V
DD
+6
Input Signal Amplitude
V
SIG
500 mVp-p (typ.), 572 mV
P-P
(max.)
Functions
鈥?/div>
680-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Auto bias circuit
Input center bias circuit.
Sample and hold circuit
Tripling PLL circuit
Inverted output
CXL5513M
8 pin SOP (Plastic)
CXL5513P
8 pin DIP (Plastic)
V
鈥?/div>
Operating temperature Topr
鈥?0 to +60
擄C
鈥?/div>
Storage temperature Tstg
鈥?5 to +150
擄C
鈥?/div>
Allowable power dissipation
P
D
CXL5513M 350
mW
CXL5513P 480
mW
Recommended Operating Range
(Ta=25 藲C)
V
DD
5 V鹵5 %
Recommended Clock Conditions
(Ta=25 藲C)
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Input clock amplitude V
CLK
400 mVp-p (Typ.)
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Clock frequency
f
CLK
3.579545 MHz
鈥?Input clock waveform Sine wave
Block Diagram and Pin Configuration
(Top View)
V
DD
VCO OUT
Structure
CMOS-CCD
VCO IN
CLK
8
7
6
5
PLL
Auto-bias circuit
Timing circuit
CCD
(680bit)
Output circuit
(S/H 1 bit)
Bias circuit
Clock driver
Bias circuit A
Bias circuit B
1
IN
2
AB
3
OUT
4
V
SS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E93Y20-TE

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