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CXL5512M Datasheet

  • CXL5512M

  • CMOS-CCD 1H Delay Line for NTSC

  • 9頁

  • SONY   SONY

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CXL5512M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5512M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for NTSC signals including
the external lowpass filter.
Features
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Single 5 V power supply
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Low power consumption
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Built-in peripheral circuit
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Built-in tripling PLL circuit
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Sync tip clamp mode
Absolute Maximum Ratings
(Ta=25 擄C)
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Supply voltage
V
DD
+6
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Operating temperature Topr
鈥?0 to +60
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Storage temperature Tstg
鈥?5 to +150
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Allowable power dissipation
P
D
CXL5512M
350
CXL5512P
480
Recommended Operating Range
(Ta=25 藲C)
V
DD
5 V鹵5 %
Recommended Clock Conditions
(Ta=25 藲C)
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Input clock amplitude V
CLK
400mVp-p (Typ.)
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Clock frequency
f
CLK
3.579545
MHz
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Input clock waveform Sine wave
Block Diagram and Pin Configuration
V
DD
VCO OUT
VCO IN
CLK
CXL5512M
8 pin SOP (Plastic)
CXL5512P
8 pin DIP (Plastic)
Input Signal Amplitude
V
SIG
500mVp-p (typ.), 572 mVp-p (max.)
(at internal clamp condition)
Functions
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680-bit CCD register
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Clock driver
Auto-bias circuit
Sync tip clamp circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
V
擄C
擄C
mW
mW
Structure
CMOS-CCD
8
7
6
5
PLL
Auto-bias circuit
Timing circuit
CCD
(680bit)
Output circuit
(S/H 1 bit)
Clamp circuit
Clock driver
Bias circuit A
Bias circuit B
1
IN
2
AB
3
OUT
4
V
SS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E93Y19-TE

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