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Input clock waveform Sine wave
Blook Diagram and Pin Configuration
(Top View)
AB
V
DD
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 527mVp-p (Max.)
(at internal clamp condition)
VGA
6
8
7
Auto-bias circuit
Bias circuit
Timing circuit
CCD
(453bit)
Clock driver
Bias circuit (A)
Output circuit
(S/H 1bit)
Bias circuit (B)
Clamp circuit
1
2
3
4
VGB
OUT
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
V
SS
IN
CLK
5
E90908A7X-PS
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