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CXL5506P Datasheet

  • CXL5506P

  • CMOS-CCD 1H Delay Line for PAL

  • 9頁

  • SONY   SONY

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CXL5506M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5506M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
鈥?/div>
Single 5V power supply
鈥?/div>
Low power consumption 95mW (Typ.)
鈥?/div>
Built-in peripheral circuits
Functions
鈥?/div>
1130-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
Auto-bias circuit
鈥?/div>
Input clamp circuit
鈥?/div>
Sample-and-hold circuit
Structure
CMOS-CCD
CXL5506M
8 pin SOP (Plastic)
CXL5506P
8 pin DIP (Plastic)
Absolute Maximum Ratings
(Ta = 25擄C)
鈥?/div>
Supply voltage
V
DD
6
V
鈥?/div>
Operating temperature Topr
鈥?0 to +60
擄C
鈥?/div>
Storage temperature Tstg
鈥?5 to +150 擄C
鈥?/div>
Allowable power dissipation
P
D
CXL5506M
350
mW
CXL5506P
480
mW
Recommended Operating Condition
(Ta = 25擄C)
Supply voltage
V
DD
5 鹵 5%
V
Recommended Clock Conditions
(Ta = 25擄C)
鈥?/div>
Input clock amplitude V
CLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
鈥?/div>
Clock frequency
f
CLK
17.734475
MHz
鈥?/div>
Input clock waveform Sine wave
Blook Diagram and Pin Configuration
(Top View)
AB
V
DD
Input Signal Amplitude
V
SIG
575mVp-p (Max.) (at internal clamp condition)
VG1
CLK
5
Timing circuit
Clock driver
Bias circuit (A)
Output circuit
Bias circuit (B)
4
8
7
6
Auto-bias circuit
Bias circuit
CCD
(1130bit)
(S/H 1bit)
Clamp circuit
1
2
3
VG2
OUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
V
SS
IN
E90632B7X-PS

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