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CXL5505P Datasheet

  • CXL5505P

  • CMOS-CCD 1H Delay Line for PAL

  • 9頁

  • SONY   SONY

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CXL5505M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5505M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
鈥?/div>
Single 5V power supply
鈥?/div>
Low power consumption 100mW (Typ.)
鈥?/div>
Built-in peripheral circuits
鈥?/div>
Built-in quadruple PLL circuit
Functions
鈥?/div>
1130-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
Auto-bias circuit
鈥?/div>
Input clamp circuit
鈥?/div>
Sample-and-hold circuit
鈥?/div>
PLL circuit
Structure
CMOS-CCD
CXL5505M
14 pin SOP (Plastic)
CXL5505P
14 pin DIP (Plastic)
Absolute Maximum Ratings
(Ta = 25擄C)
鈥?/div>
Supply voltage
V
DD
6
V
鈥?/div>
Operating temperature Topr
鈥?0 to +60
擄C
鈥?/div>
Storage temperature Tstg
鈥?5 to +150 擄C
鈥?/div>
Allowable power dissipation
P
D
CXL5505M
400
mW
CXL5505P
800
mW
Recommended Operating Condition
(Ta = 25擄C)
Supply voltage
V
DD
5 鹵 5%
V
Recommended Clock Conditions
(Ta = 25擄C)
鈥?/div>
Input clock amplitude V
CLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
鈥?/div>
Clock frequency
f
CLK
4.433619
MHz
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Input clock waveform Sine wave
Input Signal Amplitude
V
SIG
575mVp-p (Max.) (at internal clamp condition)
Blook Diagram and Pin Configuration
(Top View)
VCO IN
PC OUT
CLK
8
PLL
Timing circuit
Bias circuit (A)
Output circuit
(S/H 1bit)
Clamp circuit
Bias circuit (B)
7
V
DD
14
13
AB
12
11
10
Auto-bias circuit
CCD
(1130bit)
Clock driver
1
2
3
4
5
VG2
V
SS
IN
OUT
VG1
V
SS
V
DD
9
6
V
SS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
VCO OUT
E90731B7X-PS

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