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CXL5504M Datasheet

  • CXL5504M

  • CMOS-CCD 1H Delay Line for NTSC

  • 11頁(yè)

  • SONY   SONY

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CXL5504M/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
鈥?/div>
Single power supply (5V)
鈥?/div>
Low power consumption 90mW (Typ.)
鈥?/div>
Built-in peripheral circuits
鈥?/div>
Clamp level of I/O signal can be selected
Functions
鈥?/div>
905-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
Autobias circuit
鈥?/div>
Input clamp circuit
鈥?/div>
Sample and hold circuit
Structure
CMOS-CCD
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
Absolute Maximum Ratings
(Ta = 25擄C)
鈥?/div>
Supply voltage
V
DD
6
V
鈥?/div>
Operating temperature Topr
鈥?0 to +60
擄C
鈥?/div>
Storage temperature Tstg
鈥?5 to +150 擄C
鈥?/div>
Allowable power dissipation
P
D
CXL5504M
350
mW
CXL5504P
480
mW
Recommended Operating Condition
(Ta = 25擄C)
Supply voltage
V
DD
5 鹵 5%
V
Recommended Clock Conditions
(Ta = 25擄C)
鈥?/div>
Input clock amplitude V
CLK
0.4 to 1.0
Vp-p
(0.5Vp-p typ.)
鈥?/div>
Clock frequency
f
CLK
14.318182
MHz
鈥?/div>
Input clock waveform Sine wave
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
Blook Diagram and Pin Configration
(Top View)
CLK
5
Timing circuit
Clock driver
Bias circuit (A)
Output circuit
(S/H 1bit)
Clamp circuit
I/O control
Bias circuit (B)
4
8
7
6
Autobias circuit
Bias circuit
CCD
(905bit)
1
2
3
IN
I/O2
OUT
I/O1
V
DD
AB
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
V
SS
E89931C79-PS

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