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CXL5502P Datasheet

  • CXL5502P

  • CMOS-CCD 1H Delay Line for NTSC

  • 13頁(yè)

  • SONY   SONY

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CXL5502M/N/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5502M/N/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
The ICs contain a PLL circuit (quadruple progression).
Features
鈥?/div>
Single power supply (5V)
鈥?/div>
Low power consumption 95mW (Typ.)
鈥?/div>
Built-in peripheral circuits
鈥?/div>
Clamp level of I/O signal can be selected
鈥?/div>
Built-in quadruple PLL circuit
Functions
鈥?/div>
905-bit CCD register
鈥?/div>
Clock driver
鈥?/div>
Autobias circuit
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Input clamp circuit
鈥?/div>
Sample and hold circuit
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PLL circuit (quadruple progression)
Structure
CMOS-CCD
CXL5502M
14 pin SOP (Plastic)
CXL5502N
16 pin SSOP (Plastic)
CXL5502P
14 pin DIP (Plastic)
Absolute Maximum Ratings
(Ta = 25擄C)
鈥?/div>
Supply voltage
V
DD
6
V
鈥?/div>
Operating temperature Topr
鈥?0 to +60
擄C
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Storage temperature Tstg
鈥?5 to +150 擄C
鈥?/div>
Allowable power dissipation
P
D
CXL5502M
400
mW
CXL5502N
260
mW
CXL5502P
800
mW
Recommended Operating Condition
(Ta = 25擄C)
Supply voltage
V
DD
5 鹵 5%
V
Recommended Clock Conditions
(Ta = 25擄C)
鈥?/div>
Input clock amplitude V
CLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
鈥?/div>
Clock frequency
f
CLK
3.579545
MHz
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Input clock waveform Sine wave
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E89930E79-PS

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