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CXL5005M Datasheet

  • CXL5005M

  • CMOS-CCD 1H Delay Line for NTSC with PLL

  • 8頁

  • SONY   SONY

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CXL5005M/P
CMOS-CCD 1H Delay Line for NTSC with PLL
Description
The CXL5005M/P are general-purpose CCD delay
line ICs which provide 1H delay time of NTSC.
Features
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Low power consumption 90mW (Typ.)
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Small size package (14-pin SOP, DIP)
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Low differential gain DG = 3% (Typ.)
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Input signal ampiitude 180 IRE (= 1.28Vp-p, max.)
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Low input clock amplitude operation 200mVp-p (Min.)
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Built-in triple PLL circuit
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Built-in peripheral circuits (clock driver, timing
generator, auto-bias and output circuits)
Functions
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680-bit CCD register
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Clock drivers
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Autobias circuit
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Sync tip clamp circuit
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Sample-and-hold circuit
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PLL (triple)
Structure
CMOS-CCD
Absolute Maximum Ratings
(Ta = 25擄C)
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Supply voltage
V
DD
11
V
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Supply voltage
V
CL
6
V
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Operating temperature
Topr 鈥?0 to +60 擄C
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Storage temperature
Tstg 鈥?5 to +150 擄C
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Allowable power dissipation P
D
CXL5005M 400 mW
CXL5005P 800 mW
Recommended Operating Conditions
Supply voltage
V
DD
9 鹵 5%
V
V
CL
5 鹵 5%
V
Recommended Clock Conditions
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Input clock amplitude
V
CLK
200mVp-p to 1.0Vp-p
(300mVp-p typ.)
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Clock frequency
f
CLK
3.579545MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5005M
14 pin SOP (Plastic)
CXL5005P
14 pin DIP (Plastic)
鈥?鈥?/div>
E88Z40A79-PS

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