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CXK77Q36B160GB Datasheet

  • CXK77Q36B160GB

  • MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SR...

  • 25頁(yè)

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Description
CXK77Q36B160GB
28/33/4
Preliminary
16Mb LW LS R-R HSTL High Speed Synchronous SRAM (512K x 36)
The CXK77Q36B160GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 524,288 words
by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer
onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-
viding a high-performance user interface.
Two distinct R-R modes of operation are supported, selectable via the M2 mode pin. When M2 is 鈥渉igh鈥? this device functions
as a conventional R-R SRAM, and pin 4P functions as a conventional SA address input. When M2 is 鈥渓ow鈥? this device functions
as a Late Select (LS) R-R SRAM, and pin 4P functions as a Late Select SAS address input.
When Late Select R-R mode is selected, the SRAM is divided into two banks internally. During write operations, SAS is reg-
istered in the same cycle as the other address and control signals, and is used to select to which bank input data is ultimately
written (through one stage of write pipelining). During read operations, SAS is registered one full clock cycle after the other
address and control signals, and is used to select from which bank output data is read.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K
(Input Clock).
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after all address and control
input signals (except SAS) are registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after all address and control input
signals (including SAS) are registered.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and V
SS
, the impedance of all data output drivers can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 350 MHz operation is obtained from a single
2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
3 Speed Bins
-28
-33
-4
Cycle Time / Access Time
2.8ns / 1.5ns
3.3ns / 1.6ns
4.0ns / 1.8ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single 2.5V power supply (V
DD
): 2.5V
鹵
5%
Dedicated output supply voltage (V
DDQ
): 1.5V typical
HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.75V typical
Register - Register (R-R) read protocol
Late Write (LW) write protocol
Conventional or Late Select (LS) mode of operation, selectable via dedicated mode pin (M2)
Full read/write coherency
Byte Write capability
Two cycle deselect
Differential input clocks (K/K)
Asynchronous output enable (G)
Programmable output driver impedance
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-R and R-R w/ LS, rev 1.0
1 / 25
October 18, 2001

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