音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CXK77P36R160GB Datasheet

  • CXK77P36R160GB

  • MEMORY-UHS Synch SRAMs＜/A＞＜I＞ 16Meg Ultra-High-Speed Syn...

  • 241.10KB

  • 22頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

SONY
廬
Description
CXK77P36R160GB / CXK77P18R160GB
3/33/4
Preliminary
16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
The CXK77P36R160GB (organized as 524,288 words by 36 bits) and the CXK77P18R160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)
read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K
differential input clock.
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after address is registered.
Sleep (power down) capability is provided via the ZZ input signal.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and V
SS
, the impedance of all data output drivers can be precisely controlled.
333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of
IEEE standard 1149.1 protocol.
Features
鈥?/div>
3 Speed Bins
-3
-33
-4
Cycle Time / Access Time
3.0ns / 1.8ns
3.3ns / 1.9ns
4.0ns / 2.0ns
鈥?Single 2.5V power supply (V
DD
): 2.5V
鹵
5%
鈥?Dedicated output supply voltage (V
DDQ
): 1.8V
鹵
0.1V
鈥?HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.9V typical
鈥?Register - Register (R-R) read protocol
鈥?Late Write (LW) write protocol
鈥?Full read/write coherency
鈥?Byte Write capability
鈥?Differential input clocks (K/K)
鈥?Asynchronous output enable (G)
鈥?Sleep (power down) mode via dedicated mode pin (ZZ)
鈥?Programmable output driver impedance
鈥?JTAG boundary scan (subset of IEEE standard 1149.1)
鈥?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-R, rev 1.0
1 / 22
June 24, 2002

CXK77P36R160GB相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！