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CXK77P36L80GB Datasheet

  • CXK77P36L80GB

  • MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 8Meg Ultra-High-Speed Syn...

  • 25頁

  • ETC

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SONY
廬
Description
CXK77P36L80GB
4/42/43/44
Preliminary
8Mb LW R-L HSTL High Speed Synchronous SRAMs (256K x 36)
The CXK77P36L80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words
by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output latches, and a one-deep write buffer
onto a single monolithic IC. Register - Latch (R-L) read operations and Late Write (LW) write operations are supported, pro-
viding a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K
(Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and V
SS
, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
4 Speed Bins
-4 (-4A) (-4B)
-42 (-42A) (-42B)
-43 (-43A) (-43B)
-44
鈥?Single 3.3V power supply (V
DD
): 3.3V
鹵
5%
鈥?Dedicated output supply voltage (V
DDQ
): 1.9V typical
鈥?Extended HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.85V typical
鈥?Register - Latch (R-L) read operations
鈥?Late Write (LW) write operations
鈥?Full read/write coherency
鈥?Byte Write capability
鈥?One cycle deselect
鈥?Differential input clocks (K/K)
鈥?Asynchronous output enable (G)
鈥?Programmable impedance output drivers
鈥?Sleep (power down) mode via dedicated mode pin (ZZ)
鈥?JTAG boundary scan (subset of IEEE standard 1149.1)
鈥?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
Cycle Time / Access Time
4.0ns / 3.9ns (3.8ns) (3.7ns)
4.2ns / 4.2ns (4.1ns) (4.0ns)
4.3ns / 4.5ns (4.4ns) (4.3ns)
4.4ns / 4.7ns
8Mb LW R-L, rev 1.1
1 / 25
November 3, 2000

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